Hardware security, real-time photonic sensing, and applied AI — built to survive contact with the lab bench.
I build secure, low-latency systems where silicon meets physics — and data meets scientists.
I'm an Assistant Research Professor at the Institute for Applied AI Innovation (AAII) at The University of Texas at El Paso. My work centers on hardware security and cryptographic hardware on reconfigurable platforms — post-quantum KEMs, elliptic-curve and AES cores on FPGA — alongside signal/image processing and cloud-based AI/ML systems.
Before UTEP I was a Research Fellow at Florida Tech's Computational Mathematics & Data Science Center, building an AI-assisted, cloud-native repository for large-scale medical datasets on AWS S3 and Databricks. Earlier I spent two years at Lawrence Berkeley National Laboratory designing a GPU-accelerated Optical Frequency Domain Reflectometry platform with custom FPGA IP on the AMD Xilinx RFSoC 4x2 — <10 ms latency for distributed fiber-optic sensing. My Ph.D. at Concordia was on secure lossless image steganography, co-designed in hardware on Zynq-7000 SoCs.
Originally from Irbid, JO; grad school in Montréal, QC; currently in El Paso, TX. Off-hours: reading, gaming, building PCs, cooking, long drives, beach.
End-to-end distributed fiber-optic sensing with <10 ms feedback. Custom FPGA IP on the AMD Xilinx RFSoC 4x2 — DDR4, DMA, ADC/DAC, PCIe, QSFP28 links, tunable-laser sync. Validated on fiber-under-test setups with localized and distributed heating / strain experiments.
Compact, spec-compliant HQC-128 KEM (keygen + encaps + decaps in one time-shared datapath, KAT-validated), ultra-compact X25519/Ed25519 and Koblitz-curve scalar multipliers, and composite-field AES with the linear layer offloaded to DSP slices — all DSP/BRAM-lean on Artix-7 / Zynq.
CMDS Center. Scalable storage on Amazon S3; Databricks for distributed, analysis-ready processing. Natural-language dataset discovery; extensible analytics with built-in apps and user-defined containerized pipelines under secure governance.
A secure, lossless modulus-based image-steganography model with pipelined FPGA realization on Zynq-7000. Reconfigurable cores for AES, ECC over GF(2ⁿ), and Paillier — optimized for real-time embedded deployment.
RTL (VHDL / Verilog) modules and verification testbenches for satellite communication and payload control — timing, redundancy, and fault-tolerance under aerospace-grade constraints.
Reading, gaming, building PCs, cooking — and exploring cuisines. Middle Eastern, Italian, Thai, Japanese.